Pv partial shading module connected to grid
I need model in pv partial shading connected to grid Model consist of pv arrays connected in series and each pv connected with bypass diode then connected DC-Dc...
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Computer system expert needed
If you are a computer system expert with at least five years of experience in C, scripting, kernel programming, RTOS, FPGA, SOC, and Soft-core processors. The g...
Read moreimage processing -- 5
I want Architecture of sobel edge detection and its implementation on fpga
Read morePump control system for Fire systems project
Hello, everyone. I need an engineering for PLC. Programming Unitronic plc. https://ucarecdn.com/b4d4bdb3-0180-4d19-9710-a29b4b664393/ Here is detail. If you can...
Read moreimage processing -- 4
I am doing project on sobel edge detection on images which will be implemented in FPGA so i need architecture for sobel edge detection which will detect the edg...
Read moreNEXTION HMI GUI Design
Design GUI for Nextion HMI Display
Read moreMulti-cycle MIPS processor
A multi-cycle processor that works for specific MIPS instructions. The most important is that Control Unit must be implemented using FSM. It must have a top-lev...
Read morehfss project -- 2
designing a rectangular microstrip patch antenna with showing gain vs freq. in s11 and radiation pattern, E-plane & H-plane etc.
Read moreVivado model -- 2
(PLEASE Don't make bid before you read) I developed a verilog code for data recovery using some techniques and I want to analyse the output in Vivado and measur...
Read moreCRC-7 FPGA Verilog Implementation
Implement CRC-7 checker module using Verilog HDL (no IP cores) and the test bench, that provides sufficient testing for the module. Consider naming the module s...
Read moreSimulating a Combinational Logic Circuit
To demonstrate that custom circuit on a chip that represent a Boolean function can be implemented using a gate array chip made of only NAND gates
Read moreethereum bit stream
i have fpga vcu1525 card, so i want ether bit stream, is urgent and very serious project, so If anyone can make this project let them contact.
Read moreVivado model
(Don't make bid before you read) I developed a verilog code for data recovery using some techniques and I want to analyse the output in Vivado and measure the n...
Read moreVerilog Project
Please message me. Super easy project. I have part of it made and just need a couple of parts added.
Read moreNeed an expert in VHDL
Need an expert in VHDL for cache controller design
Read moreNeed a VHDL expert in memory controller design
Need help in designing Cache controller
Read moreHelp in Vivado code
Don't make bid before you read. Developed a verilog code for data recovery using some techniques and I want to analyse the output in Vivado
Read moreMathematical model/simulation for timing noise
Are you familiar with modelling clock and data recovery ? I have a Verilog model and I want to measure the jitter that I injected in the Tx clock? I have a Veri...
Read moreMy HPS first project
Project objective: to successfully upload the application from the uSD card DE10-Nano EVM board. The application will automatically boot up when applying power....
Read moreQuartus, Memory module, memory blocks, FPGA technology, VHDL, vhd
RAM: 1-port RAM: 2-port SRAM Block, IP Catalog, Basic functions I need QAR files
Read moreLabVIEW coder
Penguin species detection using machine learning (lab view)
Read morevhdl & fpga programing
tutor for my classes in vhdl programming and fpga programming for university
Read moreConnecting Oscillospose using UDP protocol in LabView
I have a software build for UDP protocol using LabView. You need to build a LeCroy Waverunner6zi oscilloscope model in LabView and test with UDP protocol softwa...
Read moreReconOS | FreeRTOS | Partial reconfiguration
I am looking for experts having great experience in C, scripting, kernel programming, RTOS, FPGA, SOC, and Soft-core processors. Work is divided in following pa...
Read moreDraw a op amp circuit in SiMetrix
I require an op amp circuit to be drawn like the one in the attachment. The current needs to be 1nAmp as shown in the attachment. The output figure once the sch...
Read moreSingle-Cycle Small16 Processor Datapath and Control -- 2
You need to add code to the datapath.vhd file (much of it is missing) and add the four instructions to the control.vhd file. You should not remove any code from...
Read moreVHDL project -- 2
Hi, I have a simple project that has to be implemented using VHDL. Please message me so I can send you files. Quote once you have checked the files. Regards,
Read moreProject: Microcontroller Communication over Ethernet. Need an expert on Verilog coding. -- 2
Project: Microcontroller Communication over Ethernet Subject: Data transfer between two zybo boards which are connected to laptop. Software: Vivado 2018.3 Hardw...
Read moreProject: Microcontroller Communication over Ethernet. Need an expert on Verilog coding.
Project: Microcontroller Communication over Ethernet Subject: Data transfer between two zybo boards which are connected to laptop. Software: Vivado 2018.3 Hardw...
Read moreLooking For FPGA Expert
This project is work on one video conference project using FPGA Board. Further details will be shared later ... Interested candidate feel free to chat
Read moreVerilog Code for 7-stages MIPS processor -- 2
1. Complete the modelling of design solution in Verilog HDL. 2. Obtain a bug-free compiled HDL code of the design solution. 3. Write the Verilog testbench to si...
Read morebuilding of sobel edge detection architecture in fpga.
Basically I need sobel Edge detector filter which will detect the edge of images, so i want some code or architecture in FPGA which will detect edges when i ins...
Read moreVHDL project
Hi, I have a VHDL project that I want to implement on my FPGA board. Please quote price once you have reviewed the project. Kind Regards,
Read moreLogical Design: Wireless sensor network.
Logical Design: Wireless sensor network. o Logical layout and implementation of the WSN deployment (You must show the overall connectivity between the different...
Read moreLooking for Senior FPGA expert
FPGA development of image processing system We are in the final stages of development By adding personnel Because I want to improve the development system. Requ...
Read moreHiring Computer System/Architecture Engineers for Multiple Projects
I am looking for expert engineers in following areas: 1) Computer Architecture 2) FPGA / Xilinx 3) VHDL/ Verilog 4) ROS (Robot Operating System) / Drivers 5) Li...
Read moreFPGA VHDL Design
I want a VHDL code and draw the finite state machine for the attached assignment ? I want someone expertise in FPGA VHDL design and also need explanation on how...
Read moredebug my verilog code and transfer it from Modelsim to Vivado
I have a verilog code for CDR and I want to debug it, it has small errors and maybe some fundamental errors too
Read moreMathematical model/simulation for timing noise -- 3
I have a verilog code for clock recovery and I want to measure the jitter that I injected + debug the code
Read moredeisgn using labview
Design and Implementation of an Industrial Internet of Things based SCADA system for petroleum pipeline systems.
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