Mathematical model/simulation for timing noise

Are you familiar with modelling clock and data recovery ? I have a Verilog model and I want to measure the jitter that I injected in the Tx clock?

I have a Verilog code for clock recovery and I want to measure the jitter.

I do have a Verilog model for CDR using DLL for Manchester code. I injected random jitter in the Tx clk and would like to measure it in the output.

Read the attached Research article, I have this already developed on Verilog but DLL not PLL. I already did the Verilog code, my concern is the jitter measurements. Replace VCO with buffers