Verilog Code for 7-stages MIPS processor -- 2
Budget: $30 – $250 USD
1. Complete the modelling of design solution in Verilog HDL.
2. Obtain a bug-free compiled HDL code of the design solution.
3. Write the Verilog testbench to simulate the obtained design.
4. Conduct unit testing and integration testing of the design.
5. Evaluate the deep pipeline using test codes and the Active HDL simulator.
maybe this code will help you ( it's a code for 5-stages )
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-1.html
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-2.html
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-3.html
2. Obtain a bug-free compiled HDL code of the design solution.
3. Write the Verilog testbench to simulate the obtained design.
4. Conduct unit testing and integration testing of the design.
5. Evaluate the deep pipeline using test codes and the Active HDL simulator.
maybe this code will help you ( it's a code for 5-stages )
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-1.html
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-2.html
https://www.fpga4student.com/2017/06/32-bit-pipelined-mips-processor-in-verilog-3.html