CRC-7 FPGA Verilog Implementation

Implement CRC-7 checker module using Verilog HDL (no IP cores) and the test bench, that provides sufficient testing for the module. Consider naming the module signals as clk, rst, check (for input enable), data_in (for message + CRC), out (message check result).
If you know how to develop a CRC module capable of 1 bit error correction, then tell me your considerations and probably we can change the polynomial.