Looking for Senior FPGA expert
Budget: $250 – $750 USD
FPGA development of image processing system
We are in the final stages of development
By adding personnel
Because I want to improve the development system.
Required skills:
Those who can use Xilinx tools (Vivado) in detail
Skills to have:
Those who have used Xilinx's ZYNC
Language is VHDL
ok with verilog HDL
-------------------------------
The content differs depending on whether you are at home or resident,
Of the IPs used this time, there is an IP of the purchased item.
Since the IP is a network license, you basically need to work in your network environment.
If you ask remotely, I would like to ask for some submodules,
As I wrote earlier, the design period is quite short.
The contents that can be requested at home are related to No. 1 USB.
A: CPU board
B: Touch panel
C: In-house board
Use by connecting with A-B
To control B when A stops
Connect to A-C-B and give B a repeater function and a host function to control B from C under certain conditions.
This is the content to be implemented in B.
If you wish, it will be finished in about a week.
The device is ZYNC UltraScale +.
The tool is Vivado.
Detailed specifications can be sent separately.
I made it halfway using VIVADO's HLS etc.
At the moment, the degree of completion is about 20%.
If you have experience designing USB hosts and devices in the past,
We look forward to working with you.
Regarding resident projects, we are currently in the process of verifying the operation of FPGA.
If you connect the signal to CHIPSCOPE at once, it will take 2 to 3 hours to compile.
We divide the signals into small pieces, connect the signals, and verify while working in parallel with several people.
We would like to ask for your support in this area.
Depending on the situation, we may ask you to modify or create additional modules.
The verification period of the board is from October 1st to October 9th.
From October 11th, we plan to move to the system connection test.
If a problem occurs during the system connection test, we will correct it each time.
Thank you for your consideration.
We are in the final stages of development
By adding personnel
Because I want to improve the development system.
Required skills:
Those who can use Xilinx tools (Vivado) in detail
Skills to have:
Those who have used Xilinx's ZYNC
Language is VHDL
ok with verilog HDL
-------------------------------
The content differs depending on whether you are at home or resident,
Of the IPs used this time, there is an IP of the purchased item.
Since the IP is a network license, you basically need to work in your network environment.
If you ask remotely, I would like to ask for some submodules,
As I wrote earlier, the design period is quite short.
The contents that can be requested at home are related to No. 1 USB.
A: CPU board
B: Touch panel
C: In-house board
Use by connecting with A-B
To control B when A stops
Connect to A-C-B and give B a repeater function and a host function to control B from C under certain conditions.
This is the content to be implemented in B.
If you wish, it will be finished in about a week.
The device is ZYNC UltraScale +.
The tool is Vivado.
Detailed specifications can be sent separately.
I made it halfway using VIVADO's HLS etc.
At the moment, the degree of completion is about 20%.
If you have experience designing USB hosts and devices in the past,
We look forward to working with you.
Regarding resident projects, we are currently in the process of verifying the operation of FPGA.
If you connect the signal to CHIPSCOPE at once, it will take 2 to 3 hours to compile.
We divide the signals into small pieces, connect the signals, and verify while working in parallel with several people.
We would like to ask for your support in this area.
Depending on the situation, we may ask you to modify or create additional modules.
The verification period of the board is from October 1st to October 9th.
From October 11th, we plan to move to the system connection test.
If a problem occurs during the system connection test, we will correct it each time.
Thank you for your consideration.