Pulse Analysis Fpga Design Development
Development of existing VHDL design in Quartus, targeting a Cyclone IV chip. It has a functioning PCIe interface. The design takes 12 channels of 10MHz ADC data from optical detectors. There is a need for additional pulse analysis functionality and to address a bug in an output derived from a combination of the 12 data channels.
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Uart Systemverilog
I need design(through Verilog) and verification code of UART through SystemVerilog. Need it in 3 days.
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Turbo Code Encoder And Decoder For Dvb
This is a non commercial project. Implementation of Turbo Encoder and Decoder to run DVB RCS standard packets. I would need MATLAB code fixed point version and respective verilog code for the same. The results should match with each other. Refer to ETSI STANDARD on DVB RCS for turbo coding algorithm. The decoder should be MAX LOG MAP decoder
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System Verilog Alarm Clock
Design Specifications for the Alarm Clock ▪ Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23). o Whenever the “alarm set” switch is on (SW2=1), the 6-digit 7-segment display should…
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Xilinx Zynq 7020 - Vhdl/processor Application - Vivado 2019.1
I'm looking for a FPGA / Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The board is a Zedboard (Z7020) connecting to the RF front-end (MAX2771 EK). The project consists of -) Creating in baremetal application a Vivado pipeline (2019.1) to collect RF data from the MAX2771 to be transferred to the FPGA side of the Zynq SoC -) Optimise our code for GPS position real-time application (FFT / IFFT / Signal Correlation) -) Provide documentation on…
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Multi-cycle Processor Design
You are to design and implement a multi-cycle processor with the following specifications. The accumulator-based processor has a 16-bit data bus and a 13-bit address bus. This CPU has 8 instructions that are shown in Table 1. Each instruction is 16 bits wide and occupies a memory word. As shown in Table 1, instructions have a 3-bit opcode field. The remaining 13 bits of instructions form the address field. The instruction format is shown in Figure 1. A) Design and…
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