FPGA Engineer for PCIe Endpoint Emulation

Hi there,I am looking for an experienced FPGA engineer to configure a custom PCIe Endpoint emulation profile on an AMD Xilinx Artix-7 XC7A75T device (Enigma 75T form factor).I will provide a full hexadecimal configuration space dump from a physical Intel I350-T2 Server Adapter. The goal of this project is to modify a baseline PCIe core (derived from the open-source PCILeech-FPGA framework) to perfectly replicate this donor device.Project Requirements:Static & Structural Matching: Hardcode matching Vendor/Device IDs, Subsystem IDs, Class Codes, and BAR allocations from the donor profile.Capabilities Linked List: Fully reconstruct the PCIe Capabilities Linked List (MSI/MSI-X, PM, PCIe Extended Specs) to match the donor hex offsets exactly.Strict Write-Protection: Implement custom Verilog logic to explicitly block write access to all hardware-defined Read-Only configuration space slots.Shadow BRAM Implementation: Implement a full Configuration Space Shadow in BRAM with an overlay path to ensure that writable registers (Command/Status/PMCSR) accurately update and mirror host OS writes.Dynamic BME Logic: The Bus Master Enable (BME) bit must be dynamic and follow standard PCIe initialization protocols; it must NOT be hardcoded to an 'always-on' state at cold boot.MSI-X Table Replication: Correctly map and implement the MSI-X Table and Pending Bit Array (PBA) structure inside the designated BAR memory allocation to pass official driver initialization.Unique DSN Generation: Mask the physical donor card's serial number and implement a unique, non-default Device Serial Number (DSN) in the Extended Configuration space.IOMMU Compliance: Enable and fully configure ATS (Address Translation Services) and PASID capabilities within the Xilinx PCIe IP core wrapper to ensure seamless compatibility with system DMA Remapping.Timing & Latency Emulation: Emulate the hardware timing profiles and register transition latencies of the real Intel silicon chip to pass automated active-probing tests.Footprint Stripping: Mask or remove all standard Xilinx debugging endpoints, JTAG tracking signatures, and Vivado core identifier flags.PCILeech Master Interface Routing: Properly route the underlying PCILeech core Master AXI-Stream interfaces to allow transparent host memory access without disrupting the emulated state machine or device driver integrity.Final Deliverables: The final deliverable must include the complete, uncompiled Vivado Project Source Directory (all raw .v / .vhd files) along with the compiled flashable .bin file.Testing Agreement:Since I have the physical hardware here, I will run hardware diagnostics on the compiled files and can send you back any requested register test readouts or error logs for debugging tweaks. Final project approval will be granted once the firmware successfully passes local driver initialization and write-mask validation tests.Please let me know if you have experience with PCIe IP core customization, your estimated timeline, and your quote for this project. Thank you!