Zynq FPGA Embedded Control
Budget: $50 – $0 USD
I am working on a Zynq-based project and need the programmable logic side coded to handle the embedded system control tasks that my ARM cores alone cannot meet. The goal is to off-load time-critical control loops and deterministic signal routing into the FPGA fabric so the whole design stays responsive under load.
You can use Xilinx Vivado (and Vitis if you prefer to wrap software hooks) as the toolchain. I will provide the current block diagram, timing requirements, and my existing software drivers; you return synthesizable HDL, a brief test-bench that shows the control logic reacting to inputs, and the bitstream I can drop straight into my project. Clear documentation of I/O pin assignments and register maps will make integration painless.
If you have already built control logic on Zynq, especially where low-latency response and tight coupling with PS software were essential, your experience will save us both time. Let me know what development flow you plan to follow and how quickly you can turn around the first working iteration.
You can use Xilinx Vivado (and Vitis if you prefer to wrap software hooks) as the toolchain. I will provide the current block diagram, timing requirements, and my existing software drivers; you return synthesizable HDL, a brief test-bench that shows the control logic reacting to inputs, and the bitstream I can drop straight into my project. Clear documentation of I/O pin assignments and register maps will make integration painless.
If you have already built control logic on Zynq, especially where low-latency response and tight coupling with PS software were essential, your experience will save us both time. Let me know what development flow you plan to follow and how quickly you can turn around the first working iteration.