FPGA Real-Time Sobel Detection

I am building a Verilog-based, real-time Sobel edge detector that streams video from an OV7670 camera to a monitor over VGA on a Nexys A7-100T board, all within Xilinx Vivado. The architectural concept is clear, yet the project’s success now depends on rigorous simulation, validation, and concise documentation suitable for an academic submission.

Your main focus will be designing an efficient test and simulation strategy: self-checking test-benches, frame-level functional coverage, timing verification, and any other diagnostics that prove the design meets real-time performance. I am open to whichever simulation environment you consider best—whether you stay inside Vivado’s integrated simulator or introduce ModelSim, Verilator, or another workflow—provided it integrates smoothly with the existing Vivado toolchain.

Please send a detailed project proposal that outlines:
• your step-by-step verification methodology
• key milestones and expected artefacts
• any reusable IP or frameworks you plan to leverage

Expected deliverables:
• Parameterisable Verilog modules for camera capture, Sobel operator, line buffering, and VGA output
• Comprehensive, automated test-benches with clear pass/fail criteria
• Simulation logs and performance reports demonstrating real-time throughput on 640×480 @30 fps (or higher if feasible)
• A Vivado project and bitstream ready to load onto the Nexys A7-100T
• A brief design document (2-3 pages) explaining implementation choices, resource utilisation, and how results were measured

The project is time-sensitive but manageable; clear proposals that map effort to milestones will help us start quickly and finish confidently.