Zynq FPGA Firmware Design

I am integrating a Xilinx Zynq-7000 SoC into a larger product and need the programmable-logic side to act as the main embedded-control hub. The design’s sole purpose is to give the ARM processing system reliable, low-latency access to three serial buses.

The required buses are:
• UART
• SPI
• I2C

Please build a Vivado-ready hardware project that instantiates these interfaces in the PL, links each of them to the PS over AXI, and exposes clean, parameterisable ports so I can map them to my board’s pinout later. You are free to code in VHDL, Verilog, or HLS as long as the result is synthesizable and runs on a Zynq-7000 device.

Acceptance criteria
• Vivado project (2023.x preferred) opens, synthesises, and implements with no errors.
• Simple testbench proves bidirectional traffic on all three buses.
• Clear notes show pin assignments, clocking scheme, and PS–PL address map.

Deliverables
• Complete Vivado project folder with HDL/HLS source, XDC constraints, and block-diagram file if IP Integrator is used.
• Self-check testbench plus simulation scripts (ModelSim, Questa, or Vivado XSIM).
• Short README explaining build steps and resource usage.

I am ready to start immediately and will provide the exact board schematic once we agree on the approach.