FPGA SPI Slave for PWM output — iCE40 4k HX

I need an FPGA developer to complete an existing SPI slave system on an iCE40 4k HX. The RTL is mostly written and passes individual testbenches. The work is integration, cleanup, adding ECC/CRC, synthesis, and hardware testing.

**What exists:**
- SPI Mode 0 slave command processor (Verilog)
- Downstream IP with dual-port BRAM and status registers
- PWM logic-word consumer (VAK_SSE)
- Individual module testbenches (Icarus Verilog)

**What needs to be done:**
1. Design review — document the current system, identify all issues
2. Bug fixes — resolve known issues, clean up code
3. Add parameterized ECC (Hamming/Hsiao for 16/24/32-bit words) and CRCn (11/18/26-bit)
4. Write an integration testbench covering the full path (SPI → BRAM → PWM)
5. Synthesize for iCE40 4k HX (Lattice tools or Yosys/nextpnr), ≥100 MHz SPI and PWM clocks, CDC between clock domains
6. Arduino Due test sketch for hardware verification (fuzzing test)

**Requirements:**
- Verilog, iCE40 toolchain experience
- Understanding of SPI, BRAM, clock domain crossing
- English communication

**Deliverables:** Working RTL, bitstream, testbenches, change documentation, Arduino test sketch.

**Budget:** Please quote.