FPGA projects — HireLancer archive

ID / Date Listing

Portable ultrasound device

I am working on the project of a "Portable Ultrasound Sensor". I would basically want the redesign the specific paper (for more information ask me for the paper...

HL-35098828

VLSI Design : Verilog code for the Graph Convolutional Neural Networks (GCNs) module

ASIC Acceleration for Graph Convolutional Neural Networks (GCNs) The task is to write a verilog code use that instantiates the GCN module. This verilog code che...

HL-35066927

CIS_reader

Need to program an ICE40 FPGA in order to interface the CIS front end

HL-35058817

Electrical and Computer engineering expert needed

I need an expert for my project. I'll share complete details in chat

HL-35040791

HW digital system design

Implement a 4-bit full adder using four instances of a 1-bit full adder using both ModelSim and Quartus Prime. Design a 2-to-1 multiplexer using Gate level mode...

HL-35028238

Help with Zynq CAN bus with Petalinux

Help me by implementing CAN bus on Zybo board with built in CAN controller. Then, use this hardware platform to build linux with Petalinux tool. I found that my...

HL-35026616

Reading XADC channel on Xilinx Artix-7 FPGA via TCL console

I have a TCL script based testing system for my Xilinx Vivado project. I need to add new functionality into it. This will use the Artix-7 FPGA's internal ADC to...

HL-35025086

PCB Design and FPGA Expert -- 2

This project is for the pcb design, I will share the schematics in a pdf also it has an fpga that probably needs programmed.

HL-35017335

Verilog Vivado

I need a 2 second counter on switch 0, switch 1, switch 2, switch 3, switch 4. If either of these switches are open it will give logic level 1 and will feed int...

HL-35016354

verilog coding game

Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system...

HL-35016358

verilog coding game -- 2

Make the RED square move and if its hits any of the sides, then the player loses the game. Add a graphic indicating the player lost. Add a points keeping system...

HL-35001075

Create a 2 counter in verilog to flash LED

I need a 2 second counter on switch 0, switch 1, switch 2, switch 3, switch 4. If either of these switches are open it will give logic level 1 and will feed int...

HL-34986405

VHDL and FPGA Expert

Need a VHDL and FPGA Systems expert 1. To create a modular system using VHDL. 2. To use simulation and test to verify the correctness of the design. 3. To demon...

HL-34982263

simulación Xilinx ISE

Implementar, simular FFT en entorno xilinx o alguna plataforma similar , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desa...

HL-34976850

Accelerate a python code and Convert to Python Overlay on Zynq FPGA developmenmt board

HL-34968144

FPGA into MIPI CSI2 TX Driver Development

I am looking someone having experience with MIPI CSI-2 TX (FPGA to other device, not the MIPI-CSI2 Camera into FPGA) on Xilinx MPSoC Platform and Petalinux. Its...

HL-34954888

Ultrasound sensor

Hi, I am working on the making prototype of an ultrasound sensor. The project includes three evaluation boards to capture ultrasound data from the body through...

HL-34954440

8x8 booth multiplier using vhdl

i have attached the specifics of the project. need to be finished by mid november

HL-34902289

VHDL Expert Required

VHDL Expert Required Now Urgently

HL-34894637

Create a logic block diagram

I need to draw a logic block diagram for my alarm system. See attachment below.

HL-34894227

Create a Verlilog Block Diagram

The alarm system is to be applied on 3 windows and a door. Each window and the door has a sensor (switch) such that when it is opened, it will give logic level...

HL-34877379

BladeRF or LimeSDR FPGA

What i need to be done is a FPGA for BladeRF or LimeSDR, The FPGA Should LIsen on frequency For a signal with the RX BladeRF or LimeSDR Annetna and once a signa...

HL-34847036

Code design in assembly language -

I need a design on verilog hdl that implements double MIPS at the same time

HL-34838482

Creating a GUI interface on MATLAB for Zynq Zedboard 7000 development board

with the following requirements: 1. On/Off button. 2. Enter the frequency. 3. Enter the duty cycle for all the 16PWM signals. 4. Read the value on the previous...

HL-34832374

FPGA BASED ALARM SYSTEM

I have created the following project below. However it is too basic for a final year project, I need a larger scope for this project. Please provide any help ....

HL-34822977

Accelerate python code using Vivado HLS on PYNQ FPGA

HL-34820021

Project assistance required

The detailed paper of the project is attached below. The skills required for the same are MATLAB, Xilinix, Verilog.

HL-34789910

FMCW / Phased Array Radar / SDR receiver design -- 4

I am looking for a freelancer or team that has extensive expertise in RF radar design and SDR receiver design, hardware, and firmware. More details on PM. Thank...

HL-34737385

FPGA Zedboard ethernet data transfer -- 2

We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transfer...

HL-34698685

Zedboard ethernet data transfer

We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transfer...

HL-34687469

VHDL test procedure and test bench implementation

HL-34686229

VHDL designer

ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

HL-34686231

VHDL designer -- 2

ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

HL-34678826

Need to convert MATLAB code to synthesizable VHDL code

Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

HL-34661510

KawPow bitstream for VU35 FPGA

I need a bitstream and a Linux-adapted mining software for my JungleCat with VU35P from Xillien. Freelancer will provide Bitstream and I will test its hash rate...

HL-34645107

Hi Need RISC V RTL design using Verilog for ARTY 7 board

Hi I need RISC V RTL code using Verilog.

HL-34639125

Convert MATLAB code to VHDL code

Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

HL-34634495

FPGA expert

We are looking for someone that has deep experience in programming FPGA for RF instances. We have a need to send and receive over 30mbps and hoping to find some...

HL-34618150

FPGA ENGINEER for lattice crosslink-NX series -- 2

We are looking an expert over crosslink-NX to support design for a camera aggregator. We would like to hear from you, skills and experience with other projects.

HL-34616713

FPGA ENGINEER for lattice crosslink-NX series

We are looking for an expert over crosslink-NX to support the design of a camera aggregator. We would like to hear from you, about your skills and experience wi...