Reading XADC channel on Xilinx Artix-7 FPGA via TCL console
Budget: £20 – £250 GBP
I have a TCL script based testing system for my Xilinx Vivado project. I need to add new functionality into it. This will use the Artix-7 FPGA's internal ADC to read voltage on pin A0 (XADC Channel 4). I am using the Arty A7-100 FPGA board from digilent (https://digilent.com/reference/programmable-logic/arty-a7/start).
I must use TCL console to read the analogue voltage applied on pin A0. This could be done directly if the XADC has such a support in Vivado 2020.1, or via the JTAG-AXI bridge that can serve as an AXI Master. It is not clear how this can be done via TCL.
Please only reply if you have done this before or know exactly how to do this. The project is actually quite small and straight forward if you know this already. I wonder why this website does not have more specific tags related to TCL and Xilinx Vivado.
I must use TCL console to read the analogue voltage applied on pin A0. This could be done directly if the XADC has such a support in Vivado 2020.1, or via the JTAG-AXI bridge that can serve as an AXI Master. It is not clear how this can be done via TCL.
Please only reply if you have done this before or know exactly how to do this. The project is actually quite small and straight forward if you know this already. I wonder why this website does not have more specific tags related to TCL and Xilinx Vivado.