IP Integrator with Basys 3
Program the Basys 3 using the Cordic IP Integrator to generate: the hyperbolic sine and hyperbolic cosine of an angle parameters: You must enter the angle in de...
Read moreProgram the Basys 3 using the Cordic IP Integrator to generate: the hyperbolic sine and hyperbolic cosine of an angle parameters: You must enter the angle in de...
Read moreClock-Logic Domino Circuits for High-Speed and Energy Efficient Microprocessor Pipeline. https://ieeexplore.ieee.org/document/4182513
Read moreHello! I got a task at college to use the FPGA Spartan 3E board for image processing. The image data is written into the FPGA, and then the image is processed b...
Read moreThe company is searching for external collaborators to design and test a Video test pattern generator in VHDL. The module shall be configurable for different pi...
Read moreHi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?
Read moredesign beamforming antenna using standard algorithms in x86, FPGA. RF engineering and radar, 5G
Read moreSimple, well explained and not adding extra signals, written in state machine formats with VHDL. USART written as one receiver vhd file and its simple testbench...
Read moreOptimalizace fázového závěsu, převod jednoduché sekvenční a kombinační logiky do VHDL....
Read moreTurbo codes are error correction codes that are widely used in communication systems.Turbo codes exhibits high error correction capability as compared with othe...
Read more1) CNN to predict Blood pressure from PPG on Nexys A7 FPGA. 2) input to FPGA should be analog PPG signal. 3) output should be SBP and DBP values which has to be...
Read moreWe are looking for a FPGA programmer who can debug the code for FPGA circuit and code the FPGA accordingly. I have few details that all I have. Please review th...
Read moreI need a image vision and a FPGA linescan vision 2 modes One mode show the image. Another mode show the linescan mode.
Read morei2c slave model and synthesizable i2c slave
Read moreDevlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor
Read moreLooking for FPGA developer to write simple program on Intel Stratix board
Read moreI am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to...
Read moreI need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.
Read moreWe are in the need of FPGA Engineer for a SDR product. We want to maximize the Power Output of SDR (Software Defined Radio) with the use of Amplifiers. You can...
Read moreInput(Live video) is accessed from the camera connected to the board and output should be displayed in the monitor connected to the FPGA board. and output shoul...
Read moreRealizar un circuito combinacional que realice operaciones binarias con datos de 8 bits con signo (1 bit signo, 3 bits enteros, 4 bits fracción) y despliegue el...
Read moreAccessing ADC data from PL ,store in memory and reading from PS.
Read moreHi I need a expert in red pitaya.I want to design project using red pitaya
Read moreThe VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple...
Read moreWe need a VHDL designer with expertise on video processing codec.
Read moreWe need a script to automate our FPGA design flow. Preferred in tcl language 1. Set the environment 2. Grab sources from repo 3. Run simulation and regression t...
Read moreImplement a multi channel DMA data generator/logger
Read moreaccept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. option...
Read moreI need to use Xilinx IIC IP on Artix board as a master, I used it in master mode and it didn't work well (The generated signal seems to be random) I tried the I...
Read moreI need some help with my Verilog progrmaming language. Please bid if you can assist me.
Read moreTwo tasks based on verilog, serial adder and RTL for APB based protocol. More information will be shared later. Deadline - 2days[maximum] Price - 75AUD
Read moreI need a expert who can work on tiny microprocessor which consumes low power and is very fast including ADC.
Read moreHello can you help me with this project it’s going to be similar to lab 4 that I have attached. I have attached the project pdf too (CMPE_487_PROJECT.pdf 193.22...
Read moreIm working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM
Read moreIm working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM
Read moreSystem Design and VHDL expert for urgent Task
Read moreThe VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple...
Read more1010 sequence dectectorwith 20 bit frame with consecutively 3 frames with 16 bit payload and 4 bit header
Read moreWe are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure
Read moreWe are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure.
Read moreNeed a System Verilog Expert for digital logic circuit design
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