Universal Synchronous Asynchronous Reciever Transmitter - VHDL

Simple, well explained and not adding extra signals, written in state machine formats with VHDL. USART written as one receiver vhd file and its simple testbench vhd file, transmitter vhd file and its simple testbench vhd file. baud will be generic and in generic 115200 will be selected, data range is 8 bit also. In receiver sample in the middle of the signal. no parity bit exc. State machine includes idle, start, data and stop cases for receiver and tranceiver. input, data out and done tick for both and tx start are enough.There will be also simple one .vhd file two way led blinker with written in VHDL and this file's testbench. This led blink will be done as shift register. 8 bit this blinker file will be connected these USART. In this way led blink will be changeable.
a document will be written explaining USART and shift register led blinking in short also.