VLSI Implementation of Turbo Coder for LTE using Verilog HDL

Turbo codes are error correction codes that are
widely used in communication systems.Turbo codes exhibits high
error correction capability as compared with other error correction
codes. This paper proposes a Very Large Scale Integration
(VLSI) architecture for the implementation of Turbo decoder.
Soft-in-soft out decoders, interleavers and deinterleavers is used
in the decoder side which employs Maximum-a-Posteriori (MAP)
algorithm. The number of iterations required to decode the
information bits being transmitted is reduced by the use of MAP
algorithm. For the encoder part, this paper uses a system which
contains two Recursive convolutional encoders along with pseudorandom
interleaver in encoder side.The Turbo encoding and
decoding is done using Octave, Xilinx Vivado, Cadence tools.The
system is implemented and synthesized in Application Specific
Integrated Circuit (ASIC).Timing analysis has been done and
GDSII file has been generated.