Egg Timer Verilog Code
Design egg timer in verilog code as seen below. Inputs to the FPGA include: 100MHz clock, BTNL/BTNR/BTNU/BTND push buttons, SW0/SW15 slide switches. Outputs fro...
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FIR filter
Looking for help with SystemVerilog code to optimize FIR filter.
Read moreMATALB AND SIMULINK EXPERT RELATED TO COMMUNICATION SYSTEMS -- 3
Design and implement an end-to-end digital communication link over a poor-quality communication channel using MATLAB simulation software
Read moreMATALB AND SIMULINK EXPERT RELATED TO COMMUNICATION SYSTEMS -- 2
Design and implement an end-to-end digital communication link over a poor-quality communication channel using MATLAB simulation software
Read moreMATALB AND SIMULINK EXPERT RELATED TO COMMUNICATION SYSTEMS
Design and implement an end-to-end digital communication link over a poor-quality communication channel using MATLAB simulation software
Read moreVHDL Module
Project of building a VHDL program for a simplified version of image equalization. The project specifics will be handed out to you as soon as we agree on the jo...
Read moreImage Equalizer
I need an image equalizer written in VHDL language. The semplified algorithm to use should be: DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE SHIFT_LEVEL = (8...
Read more32x32 LED Adafruit matrix driven by FPGA
I am using a 32x32 LED matrix from Adafruit and I am driving it with an FPGA. I followed the tutorial they provided and I get an image initialize. Now, I am try...
Read moreI need someone to implement a full 5 stage pipeline CPU in RISC-V in Verilog.
For more details, contact me via chat
Read moreSimulate basic aritmatic calculator using VHDL
I have uploaded the file in which all the details available .
Read moreAc voltage measurement circuit
ac voltage measurement circuit and output of this circuit is in adc and send to pic16f877a
Read moreDesign 4 bits arithmetic unit that add, multiply and subtract
Design 4 bits arithmetic unit that add, multiply and subtract using PTL & Domino *****simulate using cadence***** The app takes 3 inputs A, B, and C A, and B ar...
Read moreDesign 4 bits arithmetic unit that add, multiply and subtract using PTL & Domino
Design 4 bits arithmetic unit that adds, multiply and subtract using PTL & Domino **********simulate using cadence************* The app takes 3 inputs A, B, and...
Read moreVerilog programming
Verilog programming project using Vivado. please bid if you can assist
Read moreAltera De1 SoC FPGA
Write a program using QUARTUS ALTERA to work on De1-SoC FBGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be de...
Read moreVHDL code
Need to write a VHDL code for a small program.
Read moreSmall VHDL project starting from a project
I need someone who can develop a current small project written in VHDL. It should be a game dispaying on vga monitor.
Read moreVHDL/Quartus Expert from Pakistan....
To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demons...
Read moreI need VHDL/Quartus Expert from Pakistan
To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demons...
Read moreVHDL MATLAB Voice editing
Build me augmented reality system for voice filtering using VHDL and Matlab
Read moreVerilog synthesizable code for finding cube root of fixed point 32 bit number
Deadline is 25th Nov 2021 Please help and provide verilog code with the algorithm used to find cube root of fixed point 32 bit number and the out put should be...
Read moreNoise cancellation system
Design and implement using Matlab ModelSim and Xilinx the system provided in the paper for augmented reality noise cancellation and write a report about the wor...
Read moreLooking for someone to write a scope for my project
Title of the project HDL Digital Signal Processor core for FPGA implementation Deadline is in 15 hours budget is 20$ requirement for the scope will be through t...
Read moreC band Antenna Design
Merhaba Mustafa Bey. İsmim Köksal Genç Tusaş(Tai) datalink sistemleri konusunda çalışıyorum. Numaram beşyüzkırküç yediyüzdoksanbeş ellidokuz yirmibeş. Uzun solu...
Read moreStop watch timer
I have uploaded the file in which all the details available .
Read moreVHDL CODE WITH TEST SETUP
Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perfor...
Read moreVHDL 4 Stage Pipeline Design
4-stage pipelined design in a structural/RTL manner with several modules operating simultaneously. Each module represents a pipelined stage with its interstage...
Read moreCARS PARKING SYSTEM IN VHDL (7-SEGMENT)
I want a cars parking , counter that displays the number of cars on 7segment starting from zero to 99
Read moresynopsys and cadence
need to extract the result for the verilog code regarding ASIC
Read moreverilog project
design a verilog block with the help of fsm logic
Read moreCircuit_design_Simulation
This could be a 10 hours working task, Implement a circuit capable of adding and subtracting two 1-bit binary numbers. Use DIP switches to control your inputs a...
Read moreVLSI Design
VHDL code ,ModelSim to simulate the D flip-flop , NP Domino 8-input AND circuit
Read more8-bit Addressable Latch with built in 1of 8 Decoder
I need someone to design an 8-bit Addressable Latch with built in 1 of 8 Decoder as seen in figure 1. The circuit is composed of three stages, the decoder, latc...
Read morebioimpedance
I'm working on a bioimpedance project. I want to create a VCCS, based on enhanced howland circuit. I would like to get a steady current of below 1mAmp. The curr...
Read moreTraffic Control System
Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart...
Read moreDSP Xilinx Zynq 2019.1 FPGA
This job consists of implementing into a Xilinx Zynq three pipelines into vivado 2019.1: A phase lock loop using fixed point A frequency lock loop A delay lock...
Read moreNeed a Cadence software Developer for VLSI
Hello if you have experience of Cadence software then i have some projects you would like to work . s per discussion with my guide I have finalized my project,...
Read moreCar parking system using vhdl , fpga
Car parking system counting from 0 to 99 in 7 segment using vhdl , fpga I have the code and testbensh but I have a problem when I click on the push buttons the...
Read moreNeed an expert in VHDL and System Verilog
Need an expert in VHDL and System Verilog
Read moreMatrix multiplication using C++ and OpenMP
I am practicing using OpenMP and wish to create a matrix multiplication lambda expression, that accepts an integer size parameter (matrix size is defined as 2^s...
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