DSP Xilinx Zynq 2019.1 FPGA
Budget: €750 – €1,500 EUR
This job consists of implementing into a Xilinx Zynq three pipelines into vivado 2019.1:
A phase lock loop using fixed point
A frequency lock loop
A delay lock loop
Timeline: 3 weeks
A phase lock loop using fixed point
A frequency lock loop
A delay lock loop
Timeline: 3 weeks
Related categories:
Electronics
Verilog / VHDL
Microcontroller
Electrical Engineering
Digital Signal Processing