VHDL CODE WITH TEST SETUP

Job ID: 32158793

Budget: ₹1,500 – ₹12,500 INR

Multiplication and addition of two 16 bit numbers with various resource constraints.
Below is the expression :
Y= x0h0+x1h1+x2h2.........x0h9.

You should perform the above in a specific manner in VHDL code .
For more detail find the attached file.
Related categories: Verilog / VHDL FPGA