Image Equalizer

I need an image equalizer written in VHDL language. The semplified algorithm to use should be:

DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE
SHIFT_LEVEL = (8 – FLOOR(LOG2(DELTA_VALUE +1)))
TEMP_PIXEL = (CURRENT_PIXEL_VALUE - MIN_PIXEL_VALUE) << SHIFT_LEVEL
NEW_PIXEL_VALUE = MIN( 255 , TEMP_PIXEL)

In this project the program recieve the image dimension in 2 bytes, the first one is for columns and the second one is for rows. The third byte is the first byte of the image that the program recieves in input.

Extra Notes:
1. FLOOR(LOG2(DELTA_VALUE +1)) is an integer number
2. The project should be able to process more than one image, but the input image will never change during the execution, only when the DONE signal is high
3. The module will start processing when the START signal is high. The DONE signal has to be taken at 1 when the equalized image is written in memory, and should stay at 1 until the START signal is taken to 0. So, when START becomes 1 again, the module is ready to do another round of equalization
4. Before the first image, the module needs a RESET signal... but for other images the module doesn't need the signal anymore

COMPONENT INTERFACE:
The component has to use the following interface

entity project_reti_logiche is
port (
i_clk : in std_logic;
i_rst : in std_logic; --initializes the machine ready to recieve the first START signal
i_start : in std_logic;
i_data : in std_logic_vector(7 downto 0); --input of the program
o_address : out std_logic_vector(15 downto 0);
o_done : out std_logic; --the signal that comunicates the end of the elaboration
o_en : out std_logic;
o_we : out std_logic; --WRITE ENABLE: 1 to write in memory, 0 to read from memory
o_data : out std_logic_vector (7 downto 0)
);
end project_reti_logiche;