FPGA projects — HireLancer archive

ID / Date Listing

verilog coding using ModelSim

looking for some help with my verilog coding project using ModelSim. please bid if you can

Simulate basic aritmatic calculator using VHDL -- 2

I need this mini project in VHDL with all displayed on display. YouTube link is there for calculator help to understand. According to that program it. https://y...

HL-32252689

I am hiring Electrical & Electronics Engineers from PAKISTAN

Assalam o alaikum !!! I am hiring electrical engineers for working on my projects in following areas of electrical & electronics engineering: 1) FPGA (VHDL/Veri...

HL-32251818

VHDL CODE WITH TEST SETUP -- 2

Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perfor...

HL-32250725

VHDL/Verilog Project -- 2

Please message me for details.

HL-32243561

Carry Save Adder Systemverilog

Hey, I am looking to implement a carry-save adder in System verilog

HL-32240081

Needed a VHDL programmer

Needed a VHDL programmer having experience with multisim or any vhdl programming software.

HL-32234332

System Verilog Project

Need help with improving an existing system verilog code. Reach out to me if you have experience with system verilog code.

HL-32231085

VHDL code with test bench setup (Convolution Problem)

Two 16-bit number from X0 and X9 and H0 to H9 multiply them and add them . Code shall be done in VHDL Y= x0h0+x1h1+x2h2+x3h3+........x9h9. For more details find...

HL-32225904

VHDL designer using Altera DE2 115

scrolling display message board pls use the assign ports here is the denouncer provide library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; enti...

HL-32219378

Noise filtering system ModelSim , Matlab ,Xilinx , VHDL, Embedded systems -- 3

The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also wit...

HL-32219273

Noise filtering system ModelSim , Matlab ,Xilinx , VHDL, Embedded systems -- 2

The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also wit...

HL-32218494

Verilog Egg Timer

See text attachment for project

HL-32217864

Basic calculator using vivado on basys3 fpga

To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short per...

HL-32215610

Verilog on a weekend :)

Hi, I have a couple of Verilog questions and would be happy to pay to pick someones brain! Attached is a simple HLS program that I synthesized to Verilog. I hav...

HL-32214878

Dc motor pwm , vhdl using fpga -- 3

I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit (DE10-Lite) and I need report about a project

HL-32214771

Dc motor pwm , vhdl using fpga

I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

HL-32206205

FPGA Project

1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. O...

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Adder Architecture

Need help designing an adder architecture in Verilog/Systemverilog.

HL-32202443

Verilog programming-2

Verilog programming project using Vivado. please bid if you can assist

HL-32201571

Egg Timer Verilog Code -- 2

Design egg timer in verilog code as seen below. Inputs to the FPGA include: 100MHz clock, BTNL/BTNR/BTNU/BTND push buttons, SW0/SW15 slide switches. Outputs fro...

HL-32201543

Egg Timer Verilog Code

Design egg timer in verilog code as seen below. Inputs to the FPGA include: 100MHz clock, BTNL/BTNR/BTNU/BTND push buttons, SW0/SW15 slide switches. Outputs fro...

HL-32200875

FIR filter

Looking for help with SystemVerilog code to optimize FIR filter.

HL-32196132

VHDL Module

Project of building a VHDL program for a simplified version of image equalization. The project specifics will be handed out to you as soon as we agree on the jo...

HL-32195546

Image Equalizer

I need an image equalizer written in VHDL language. The semplified algorithm to use should be: DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE SHIFT_LEVEL = (8...

HL-32189922

I need someone to implement a full 5 stage pipeline CPU in RISC-V in Verilog.

For more details, contact me via chat

HL-32184572

Verilog programming

Verilog programming project using Vivado. please bid if you can assist

HL-32184469

Altera De1 SoC FPGA

Write a program using QUARTUS ALTERA to work on De1-SoC FBGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be de...

HL-32180544

Small VHDL project starting from a project

I need someone who can develop a current small project written in VHDL. It should be a game dispaying on vga monitor.

HL-32180473

VHDL/Quartus Expert from Pakistan....

To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demons...

HL-32180480

I need VHDL/Quartus Expert from Pakistan

To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demons...

HL-32178378

Verilog synthesizable code for finding cube root of fixed point 32 bit number

Deadline is 25th Nov 2021 Please help and provide verilog code with the algorithm used to find cube root of fixed point 32 bit number and the out put should be...

HL-32165435

FPGA Coder for Financial markets

I need someone to code me FPGA for financial markets https://github.com/G-ram/HFT

HL-32158793

VHDL CODE WITH TEST SETUP

Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perfor...

HL-32156141

CARS PARKING SYSTEM IN VHDL (7-SEGMENT)

I want a cars parking , counter that displays the number of cars on 7segment starting from zero to 99

HL-32151800

verilog project

design a verilog block with the help of fsm logic

HL-32150908

VLSI Design

VHDL code ,ModelSim to simulate the D flip-flop , NP Domino 8-input AND circuit

HL-32138895

Traffic Control System

Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart...

HL-32136594

Need a Cadence software Developer for VLSI

Hello if you have experience of Cadence software then i have some projects you would like to work . s per discussion with my guide I have finalized my project,...

HL-32135733

Car parking system using vhdl , fpga

Car parking system counting from 0 to 99 in 7 segment using vhdl , fpga I have the code and testbensh but I have a problem when I click on the push buttons the...