VHDL code with test bench setup (Convolution Problem)

Job ID: 32231085

Budget: ₹1,500 – ₹12,500 INR

Two 16-bit number from X0 and X9 and H0 to H9 multiply them and add them . Code shall be done in VHDL
Y= x0h0+x1h1+x2h2+x3h3+........x9h9.

For more details find the attached Set of Question.
Related categories: Verilog / VHDL Assembly FPGA