Need an expert in Vivado HLS -- 2
Need an expert proficient in Vivado HLS
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Need an expert in Vivado HLS
Need an expert in Vivado HLS to implement median filter using C. The testbench would have to created using C itself.
Read moreFPGA PROGRAMMING - Create A Specific Algorithm
Hello, I'm hiring a dev who's very hot with FGPA. Need him to create cryptocurrency miner/blockchain. Specificly Xilinx Alveo U200 & U250 Cards. I can pay a lot...
Read moreFPGA-based implementation of a cryptographic system for IoT applications
I need to implement FPGA-based implementation of a cryptographic system for IoT applications with Xilinx FPGA. Please go through the attachments for complete de...
Read moreFMCW / Phased Array Radar / SDR receiver design -- 3
I am looking for a freelancer or team that has extensive expertise in RF radar design and SDR receiver design, hardware, and firmware. More details on PM. Thank...
Read more5G RAN FPGA Design
We have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must ha...
Read moreSetup gaming web server
I have a empty dedicated server that I would like to install a control panel to make/host instances of different games like Minecraft,rust etc....
Read moreSPI interface from a FPGA and a GPU
Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for...
Read moreI need a coder who also understands crypto
I need a coder to whom Ill provide most codes they just have to work around it and work it out, which can bring income for the coder and myself with continous w...
Read morepython to collect data
using python to collect memory timing
Read moreFMCW / Phased Array Radar / SDR receiver design -- 2
I am looking for a freelancer or team that has extensive expertise in RF radar design and SDR receiver design, hardware, and firmware. More details on PM. Thank...
Read moreEthernet RTL(Verilog) Tutor
Explain and help understand Ethernet MAC/PHY RTL from github. https://github.com/alexforencich/verilog-ethernet Required: - Industry experience in digital/mixed...
Read moreAudio and multiple threaded applications using DE-1 SOC
To create user-level Linux programs that produce audio output on the DE1-SoC board. The task is to implement a digital piano that can play musical chords throug...
Read moreFPGA program for mining of the Kaspa crypto currency
GPU cryptocurrency mining is not able to keep up with the power of FPGAs and ASIC miners. I would like to purchase FPGAs for cryptocurrency mining (at present i...
Read morebit serial multiplier and digit-serial multiplier
bit serial multiplier and digit-serial multiplier by using a Vivado 2019.1
Read moreVIDEO SDI Seamless Switcher with HDMI outputs
Design 4xSDI seamless switcher with 2 HDMI outputs which support 1080p (Full HD) In this project must use FPGA for SDI inputs with input auto-detect resolutions...
Read moreKnowledge of verilog, python and machine learning
i need to map emg, ecg, eeg data into verilog code to be mapped in FPGA later of CAP SLEEP DATABASE. Also build a python code in machine learnig model for same.
Read moreBPSK demodulation using fpga
I m looking for a fpga design for an BPSK demodulator, the fpga ill be using is altera, i ll also require an simulink file illustrating the functionality of the...
Read morefpga micro/main controller picoblaze project
I want professional electronic/electric expert who is good in microcontroller picoblaze soft, FPGA, and can do proejct in ISE and ANVYl board check the below re...
Read moreediting created FPGA Program for needle broken identification system using video processing
Hello ,I have developed following code for gowin gw1n- lv1qn48c6/15 and i want to proffesional freelancer for check and testng. We have reference images of need...
Read moreNeed a skilled programmer to develop an Eth miner for Xilinx U250 in azure vm NPsV1 -- 2
I need a FPGA programmer to build a mining solutionfor mining Ethereum with a Xilinx U250 in azure vm NPsV1 os ubuntu
Read moreCombined fully compliant OBD-II and J2534-1/2 interface
Need to design and implement an OBD-II interface to support all ratified and none-ratified OBD-II protocols, together with the Linux SocketCAN drivers. Specific...
Read moreElevator control system
Need to implement an elevator control system with top module, data path module, necessary other sub modules and a test bench.
Read moreZync DRAM Project -- 2
Zync DRAM Controller to read and write DRAMs.
Read moreCreating FPGA Program for needle broken identification system using video processing
Hello ,We have reference images of needle knitting mashing thread area. It has different color types of threads. Some times the needle is broken. We have to ide...
Read moreFMCW / Phased Array Radar / SDR receiver design
I am looking for a freelancer or team that has extensive expertise in RF radar design and SDR receiver design, hardware, and firmware. More details on PM. Thank...
Read moreCreating FPGA Program for needle broken identification system using video processing
Hello ,We have reference images of needle knitting mashing thread area. It has different color types of threads. Some times the needle are broke. We have to ide...
Read moreFPGA Expert Needed -- 2
An expert with FPGA is needed. The expert must be proficient with Quartus Prime.
Read moreCreate a native c code for crypto and then port to Xilinx
We need to port to native c++ a KDA algo that is blake2s and verify that works (so that create nounce from work) and then port this to HSL verilog (xilinx) The...
Read moreFPGA Expert Needed
An expert with FPGA is needed. The expert must be proficient with Quartus Prime.
Read moreMiner for fpga xilinx alveo u200
I need a developer who can build a miner for sha256d algo (including bitstream) for u200 fpga’s FPGA’s are located in aws data center, We could give you a ssh o...
Read moreLCD CONTROLLER
I want to a project 'stopwatch' in LCD by using FPGA kit with VHDL code. In the fires line the LCD will show the word 'Stopwatch' and counter in the next line (...
Read moreทำเครื่องคิดเลข ใช้ verilog, basys3
ขอภายใน 1 วัน? https://docs.google.com/document/d/e/2PACX-1vR-5MzdWccs4iCyi8OEAKwo8JxCRpaBjkO8c_bAMV4Cux8T9p-ZIaCn26CYwyubyEKkYue07fn1o8OL/pub?fbclid=IwAR0KQHwR...
Read moreMCP4725 interface for myr zturn-board z7020
Production of interface ip for MCP4725 for zturn-board z7020 complete of tcl files for ip creation, synyhesis and implementation
Read moreExpert in FEM / FEA / FPGA / PYTHON
Bid only if you an expert in Finite Element Method and you can also work on python at the same time. I have a task that involved FEM and python at the same time...
Read moreOptimizing Adder for better Power and Area
Hi, I am looking to optimize the area and power of my current design. Looking for a freelancer to help me achieve the same.
Read moreI need someone to implement a full 5 stage pipeline CPU in RISC-V in Verilog.
For more details, contact me via chat
Read moreDevelopment of application in RTOS for inputting spdif audio , decoding it and passing to i2ss
We want to build an application which will receive spdif input audio and decode it and send it to i2s . It is done using the kernel and in custom RTOS.
Read moreOptimize Vitis HLS Code
Hi, I am searching for a freelancer with experience in **parallelizing functions on hardware.** I wrote a fairly inefficient solution and would like to improve...
Read moreethhash bitstream
i have Xilinx FPGA BCU/VCU1525 Card, i want to bit Stream for Ethereum Coin, and i have also vivado lab 2020,
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