5G RAN FPGA Design

We have an internal project for 5G RAN FPGA design for DFE products:
Skills:
Job Description- Senior MTS RTL design 5G Product( 2 positions)

· Candidate must have at least Bachelors or Masters EE
- FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR)

· Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience

· Preferred prior project experience in 5G ORAN - RU/DU.
DSP knowledge

Matlab modeling is preferred.

· eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588

· Knowledge of Queuing theory

· Tools – Minimum 4 years of FPGA design experience – Xilinx Vivado, Intel and/or Lattice experience including Synthesis, Place and Route.

· Candidate will be responsible for programming bitfiles into FPGA on multiple FPGA platforms

· Timing Analysis – At least one Timing Analysis tools – Xilinx Vivado or Synopsys Primetime or Equivalent Cadence Tool.

· DFT – Candidate must demonstrate knowledge of implementing Scan chain synthesis, ATPG ( Synopsys or Mentor NOT Cadence). MEMBIST and Logic BIST

· Formal Verification – Minimum 2 years of Formal Verification – SNPS VC formal or Cadence Jasper Gold – RTL to Gates and Gates to Gates.

· Deep knowledge of ASIC interfacing standards such as AXI-4, Wishbone.

· Prior Experience with DRAM Interfacing is preferred

· Employees are expected to be able to work from our offices or work from home might travel to Canada