Combined fully compliant OBD-II and J2534-1/2 interface
Budget: $500 – $1,000 USD
Need to design and implement an OBD-II interface to support all ratified and none-ratified OBD-II protocols, together with the Linux SocketCAN drivers. Specification as follows:
A. Hardware:
1. Support for the full pin 1 - 16 physical layer of the J1962 connector. This is to include support for the different manufacturer-specific modes of pins 1, 9, 3, 11, 12 and 13
2. Interface needs to support the different programming voltages required on each pin, per manufacturer spec
3. Full MS-CAN, K-line, J1850 and DoIP required, per manufacturer spec
4. Interface needs to be centre around an FPGA, to allow for future feature upgrade. FPGA firmware code to be written in either SystemC (preferred) or VHDL. In either case, needs to be fully documented.
5. XC7Z020-1CLG400C FPGA (or better, from the same series) from the Xilinx lineup is to be used. Verification will be carried out on the Digilent Zybo Z7 Board. Necessary drivers and bring-up to be provided as a set of Yocto packages
B. Software/Firmware:
1. Host device for the interface detailed above shall be a BeagleBone Black device (https://beagleboard.org/black-industrial), with the interface provided as a Cape, following the hardware interface specification for said capes
2. Device drivers and full Linux source image shall be provided as a fully integrated Yocto package - this will be bundled with the lower-level firmware and drivers referred to in hardware specification in (A) above
3. All source code shall be extensively documented and provision for both production and debug version compilation provided
4. A full set J2534-1 and J2539-2 drivers for both USB (must) and 100baseTx ethernet + IP (could be a future dev). In the case of the latter, a J2354-to-IP stack shall be required - this could be a future feature.
Please refer to the attachment for a high-level representation of the requirements above.
A. Hardware:
1. Support for the full pin 1 - 16 physical layer of the J1962 connector. This is to include support for the different manufacturer-specific modes of pins 1, 9, 3, 11, 12 and 13
2. Interface needs to support the different programming voltages required on each pin, per manufacturer spec
3. Full MS-CAN, K-line, J1850 and DoIP required, per manufacturer spec
4. Interface needs to be centre around an FPGA, to allow for future feature upgrade. FPGA firmware code to be written in either SystemC (preferred) or VHDL. In either case, needs to be fully documented.
5. XC7Z020-1CLG400C FPGA (or better, from the same series) from the Xilinx lineup is to be used. Verification will be carried out on the Digilent Zybo Z7 Board. Necessary drivers and bring-up to be provided as a set of Yocto packages
B. Software/Firmware:
1. Host device for the interface detailed above shall be a BeagleBone Black device (https://beagleboard.org/black-industrial), with the interface provided as a Cape, following the hardware interface specification for said capes
2. Device drivers and full Linux source image shall be provided as a fully integrated Yocto package - this will be bundled with the lower-level firmware and drivers referred to in hardware specification in (A) above
3. All source code shall be extensively documented and provision for both production and debug version compilation provided
4. A full set J2534-1 and J2539-2 drivers for both USB (must) and 100baseTx ethernet + IP (could be a future dev). In the case of the latter, a J2354-to-IP stack shall be required - this could be a future feature.
Please refer to the attachment for a high-level representation of the requirements above.