Ethernet RTL(Verilog) Tutor
Budget: $250 – $750 USD
Explain and help understand Ethernet MAC/PHY RTL from github.
https://github.com/alexforencich/verilog-ethernet
Required:
- Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP.
Meetings will be conducted via zoom/meets.
Thank you!
https://github.com/alexforencich/verilog-ethernet
Required:
- Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP.
Meetings will be conducted via zoom/meets.
Thank you!
Related categories:
Verilog / VHDL
Semiconductor
FPGA Coding
DDR3 (PCIe, board design/fpga)
Digital ASIC Coding