System Verilog Alarm Clock

$ 30.00 — 250.00 USD

Design Specifications for the Alarm Clock
▪ Time should be displayed on the 6-digits of the 7-segment display (HHMMSS).
o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds.
(the period is not wired up in the DE0-CV board)
o Hours will be displayed in “military time” (meaning 00 through 23).
o Whenever the “alarm set” switch is on (SW2=1), the 6-digit 7-segment display should display the alarm setting rather than the current time.
o Whenever the “alarm clear” button (KEY0=0) is pressed, the alarm should be reset to 0.
o KEY0 takes priority over SW2 meaning that if it is pressed while SW2 is active, the alarm should be reset to 0.
▪ Timing / Clock generation
o The alarm clock should be accurate.
Divide down the 50MHz clock at PIN_M9 as necessary to achieve this (on the FPGA).
You are not expected to verify that your clock keeps good time.

For all Frequency dividers use a 50% duty cycle.
This should be constructed similar to a counter. 50% duty cycle means the output clock, the result of dividing down, should be logic 1 half the time and logic 0 half the time.

Do not use 50MHz for your test bench, it will not work.
Use 2Hz for simulation verification.

▪ Switch functions
o SW0=1 will act as a reset.
Both the time and the alarm time should be reset to zero if
SW0 goes active.
SW0 has priority over any other switch (reset)
o SW1 is the time_set switch, if it is set to 1 you are setting the time (time_set)
o SW2 is the alarm_set switch, if it is set to 1 you are setting the alarm (alarm_set)
o SW3=1 set hours, SW3=0 set minutes (sethrs1min0)
o SW4=1 run the clock time (run_clock)
o SW5=1 active the alarm (activatealarm)
▪ Push button functions
o KEY0 pressed (=0) causes the alarm to reset (almreset)
o KEY1 pressed (=0) sets what ever is selected, let up it stops, you want the numbers changing at a 2Hz clock rate (twice a second) (runset)
Simulation Verification
The module for simulation verification should be:

module alarm_clock(input CLK_2Hz, reset, time_set, alarm_set, sethrs1min0, run_clock, activatealarm, alarmreset, runset,
output logic sec, min, hrs, min_alrm, hrs_alrm,
output logic alrm);

Write a test bench named alarm_clock_tb that has alarm_clock as an instance.
Your test procedure should be to
1.
Do a reset
2.
Set the alarm to 5 hours and 30 minutes.
3.
Set the time to 5 hours and 29 minutes.
4.
Active the alarm and
5.
Then run time.
6.
After the alarm goes off, reset the alarm.
7.
Reset the clock.

Must be done in system verilog.

Verilog / VHDLFPGAFPGA Coding

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