Ethernet RTL(Verilog) Tutor

$ 250.00 — 750.00 USD

Explain and help understand Ethernet MAC/PHY RTL from github.
https://github.com/alexforencich/verilog-ethernet

Required:
- Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP.

Meetings will be conducted via zoom/meets.

Thank you!

Verilog / VHDLSemiconductorFPGA CodingDDR3 (PCIe, board design/fpga)Digital ASIC Coding

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