Development of PCIE and Other Protocol Verification Components -- 2

Job ID: 31976747

Budget: $250 – $750 USD

Job Description :-

Develop Verification Component of PCIE and other protocol devices including Generators, Transactors, Drivers, Transmiter, Receiver and Transmit and Receive Packet Classes.
Build Simvs, and develop and Run test-cases using these components.



Detailed Requirement :-

1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experience either in RTL Design or TB/Verification.

2) Experience in VLSI - ASIC/FPGA design with following skillset -
a) Verilog, System Verilog,
b) Perl, Bash, Make
c) working in Unix/Linux Environment and Vim/gvim


5) Time Availibility -
a) Desirable to have at least 10-15+ hours per week for the work.
b) Able to support next 1-2 months minimum.



Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.

Benefits :-
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
Related categories: Verilog / VHDL Microcontroller UNIX FPGA ASIC