Ultra Low PDP Domino Logic Design for IEEE Publication -- 2

I am seeking an experienced VLSI Research Engineer with expertise in Cadence Virtuoso, Spectre Simulation, CMOS Circuit Design, Low-Power VLSI, and IEEE Paper Writing. The task involves replicating all designs from the given reference paper, including the proposed RVLDG design, using Cadence Virtuoso and Spectre Simulator. Following this, the proposed RVLDG design must be optimized to achieve the lowest Power Delay Product (PDP) compared to all existing domino gates (Conventional Domino Gate, SARDDG, HSCDDKDG, and RVLDG). The novelty of the proposed architecture must be genuine and technically justified. It should be optimized primarily for minimum PDP while maintaining full-swing output and low leakage power. All claims must be supported by simulation results and comparison tables.

Deliverables include:
- Cadence Virtuoso schematics
- Testbenches
- Transient analysis outputs
- Simulation results (including Monte Carlo analysis and PVT analysis)
- PDP comparison tables
- Step-by-step explanation of the proposed design optimization process from scratch
- IEEE conference paper