TCL script for FPGA design flow automation Open
Budget: €12 – €18 EUR
We need a script to automate our FPGA design flow. Preferred in tcl language
1. Set the environment
2. Grab sources from repo
3. Run simulation and regression test
4. Run synthesis and place and route (vendor independent)
5. Generate reports
6. More than one project, we want to run it during night time
1. Set the environment
2. Grab sources from repo
3. Run simulation and regression test
4. Run synthesis and place and route (vendor independent)
5. Generate reports
6. More than one project, we want to run it during night time