A sequence Detector Design using Moore machine on EDA PLAYGROUND

Looking for an experienced and qualified Electronics Engineer with VHDL language expertise to help me in verilog description of a circuit that receives a 1-bit serial data and that detects a given binary sequence. The circuit will have a single data input that inputs a single bit every clock cycle. it has a single output that is 0 when no sequence is detected. Whenever a sequence (see table below) is detected this output goes to 1 for a single clock cycle