I need a verilog designer for making an atm model using fsm which will be implemented on cyclone V fpga
Budget: ₹600 – ₹1,500 INR
The states are Idle state, Authentication state, menu state, withdraw state, deposit state, mini statement state, extra states can be added, if necessary. Moore implementation would be ideal as it is easy to implement, the model should be able to perform contain the following:
1)Withdraw
2)Deposit
3) Mini statement (up to 4 transactions)
4)Block the account for 24hrs if an incorrect pin is entered 3 times
It is preferable if the Implementation of the STATES is done in different submodules and overall flow is controlled by the Main module containing the FSM. I/O utilization is recommended to be kept at minimum. Simulation with testbench simulation, Synthesis and Implementation is desired. Assume required power constraints and timing constraints for the model to work. Assume any other specifications if necessary.
1)Withdraw
2)Deposit
3) Mini statement (up to 4 transactions)
4)Block the account for 24hrs if an incorrect pin is entered 3 times
It is preferable if the Implementation of the STATES is done in different submodules and overall flow is controlled by the Main module containing the FSM. I/O utilization is recommended to be kept at minimum. Simulation with testbench simulation, Synthesis and Implementation is desired. Assume required power constraints and timing constraints for the model to work. Assume any other specifications if necessary.