I need verilog coding by moore or mealy for the question below
Budget: $3 – $10 SGD
Design, simulate and verify a synchronous digital system that detects and recognizes your
student ID as password that can be used to generate an output signal. The student ID is entered to the system sequentially and synchronized to the master clock for proper operation of the system. The system is expected to generate an output logic High for 3 clock cycles if the ID sequence is detected correctly. The system will then return to the wait state, where it waits for a new sequence to be entered by user. Use any of the student ID from the group members in this design. You are free to add any additional features to your system as deemed appropriate.
student ID as password that can be used to generate an output signal. The student ID is entered to the system sequentially and synchronized to the master clock for proper operation of the system. The system is expected to generate an output logic High for 3 clock cycles if the ID sequence is detected correctly. The system will then return to the wait state, where it waits for a new sequence to be entered by user. Use any of the student ID from the group members in this design. You are free to add any additional features to your system as deemed appropriate.