I need someone with good knowledge of CPU Pipelining with Cache Memory (D-Cachec and I-Cache).

I have a in-order processor design (with all the stages like Fetch, Decode, ALU, etc..) and a snippet of code which contains order of instructions (load, add...). Based on that, I need to draw chronograms for first two iteration of the given loop. I will send all the requirements via chat. The project should not take more then 2-3 hours to do.