I need VHDL designer

Job ID: 30695033

Budget: $250 – $750 USD

I need to complete my thesis project using Xilinx IDE and the topic is optimisation of QPSK on to FPGA. Dealing it with block wise. The coding needs to be done in VHDL

Related categories: Engineering Verilog / VHDL Microcontroller Electrical Engineering FPGA