20 instructions for RISC-V pipelined processor with the elimination of the hazards -- 4
Budget: $30 – $250 USD
The instruction set for the processor RISC-V should be expanded.
Hardware implementation of RISC-V processor with pipeline is already done (There is 5 stages of pipeline:
Fetch, Decode, Execute, Memory and WriteBack).
VHDL files are in attachment. The task is to upgrade this processor with 20 new instructions.
For each instructions there is possibility of appearance of the hazard.
Every hazard must be resolved. In the documentation there is explanation for the hazards as well as their elimination.
Also, in VHDL files, there is implementation of blocks which remove hazards.
Just ADD, AND, SUB and OR instructions are implemented in RISC-V.
Current implementation of RISC-V support just this 5 instructions, so update of RISC-V is need it for 20+ new instructions
For interactive simulation of RISC-V processors as well as code assembly is possible
download the “Ripes” program from the following link:
https://github.com/mortbopet/Ripes/releases
In assembly_instructions folder from attachment, there is a files for assembly instructions that should be implemented in RISC-V.
In assembly folder, there is a assembler code for instruction that you should just copy to Ripes and see how processor is behaving.
And in binary folder there is binary representation of those instructions. This binary files should be read by the VHDL RISC-V (TOP_RISCV_tb.vhd) and represent at the waves!
The 20 instructions required are chosen arbitrarily by the designer (you).
Tips:
For R-type instruction (They are easy to implement),
put NOP (no operation) instruction, and later update Forwarding unit, that should deal with hazards.
For instructions with jump/load/store, Branch forwarding will deal with hazards.
The idea is to reduce the processor bandwidth as much as possible.
Files are the skeleton of the program and most of the work (if you want to, you can write your own RISC-V),
you just need to update certain VHLD files (which are in attachment) with new instructions as well as the hazards solution.
So, for example, if you add shift instruction, you need to update ALU unit.
Also, need to explain potential problems for each instruction, test in .tb (just update, already exist).
Summary of the tasks:
- update files of RISC-V in VHDL, because that is need it when new instruction are going to be implemented
- read 20+ instructions from txt files that are in assembly_instructions folder in attachment
- document the changes
In attachment, there is RISC_V_pipelined.pdf with hazards details,
Set_Instructions_RISC-V.pdf details about the instructions and
riscv-spec-v2.2.pdf if need it.
Use Vivado 2019.1 version
To run project in Vivado follow this steps:
Open Vivado -> Tools -> Run Tcl Script (click on RISCV.tcl from RISCV_Pipelined_source_codes)
Hardware implementation of RISC-V processor with pipeline is already done (There is 5 stages of pipeline:
Fetch, Decode, Execute, Memory and WriteBack).
VHDL files are in attachment. The task is to upgrade this processor with 20 new instructions.
For each instructions there is possibility of appearance of the hazard.
Every hazard must be resolved. In the documentation there is explanation for the hazards as well as their elimination.
Also, in VHDL files, there is implementation of blocks which remove hazards.
Just ADD, AND, SUB and OR instructions are implemented in RISC-V.
Current implementation of RISC-V support just this 5 instructions, so update of RISC-V is need it for 20+ new instructions
For interactive simulation of RISC-V processors as well as code assembly is possible
download the “Ripes” program from the following link:
https://github.com/mortbopet/Ripes/releases
In assembly_instructions folder from attachment, there is a files for assembly instructions that should be implemented in RISC-V.
In assembly folder, there is a assembler code for instruction that you should just copy to Ripes and see how processor is behaving.
And in binary folder there is binary representation of those instructions. This binary files should be read by the VHDL RISC-V (TOP_RISCV_tb.vhd) and represent at the waves!
The 20 instructions required are chosen arbitrarily by the designer (you).
Tips:
For R-type instruction (They are easy to implement),
put NOP (no operation) instruction, and later update Forwarding unit, that should deal with hazards.
For instructions with jump/load/store, Branch forwarding will deal with hazards.
The idea is to reduce the processor bandwidth as much as possible.
Files are the skeleton of the program and most of the work (if you want to, you can write your own RISC-V),
you just need to update certain VHLD files (which are in attachment) with new instructions as well as the hazards solution.
So, for example, if you add shift instruction, you need to update ALU unit.
Also, need to explain potential problems for each instruction, test in .tb (just update, already exist).
Summary of the tasks:
- update files of RISC-V in VHDL, because that is need it when new instruction are going to be implemented
- read 20+ instructions from txt files that are in assembly_instructions folder in attachment
- document the changes
In attachment, there is RISC_V_pipelined.pdf with hazards details,
Set_Instructions_RISC-V.pdf details about the instructions and
riscv-spec-v2.2.pdf if need it.
Use Vivado 2019.1 version
To run project in Vivado follow this steps:
Open Vivado -> Tools -> Run Tcl Script (click on RISCV.tcl from RISCV_Pipelined_source_codes)