incremental encoder interface
Budget: €30 – €250 EUR
requiring the design of a VHDL synthesizable module to interface an incremental encoder.
This is generic ABZ quadrature decoder, some code woulc also be found on the net already, that requires integration and testing (https://www.fpga4fun.com/QuadratureDecoder.html)
The encoder is the https://www.lika.it/eng/products/rotary-encoders/incremental/c85
Z is for homing (it marks the zero position of the encoder)
specs and deliverables in the attached document
This is generic ABZ quadrature decoder, some code woulc also be found on the net already, that requires integration and testing (https://www.fpga4fun.com/QuadratureDecoder.html)
The encoder is the https://www.lika.it/eng/products/rotary-encoders/incremental/c85
Z is for homing (it marks the zero position of the encoder)
specs and deliverables in the attached document