design verification engineer
Budget: $30 – $90 USD
• Strong knowledge Design & Verification methodologies of either of these (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate
• Understanding of verification tools like Simulator, Synthesis etc.
• Hands on experience on C/C++, System Verilog, UVM, SystemC, RTL
• Understanding of some of the standard protocol interfaces like AMBA, Automotive, PCIe, USB etc.
• Excellent written and verbal interpersonal skills
• Self-motivated and great teammate