8 bit counter and BCD counter
Budget: $10 – $30 USD
-Write a VHDL file for an 8-bit counter with active-LOW asynchronous clear, active-HIGH synchronous load, active-HIGH count enable, and a directional input that makes the circuit count up when DIRECTION = 1 and down when DIRECTION = 0.
- Write a set of simulation criteria that verifies the operation of the counter. The simulation must contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable.
-Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable.
-The counter must count up from 00 to 09, then 10 to 19, and so on until it reaches 99. At that point the counter must roll over to 00. The parallel inputs should load any values from 0 to 9 on each digit. If a parallel binary input falls outside the valid BCD range (1010 to 1111) for either digit, the circuit should set that digit to 9 when the parallel input is loaded.
- Write a set of simulation criteria that verifies the operation of the counter. The simulation must contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable.
-Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable.
-The counter must count up from 00 to 09, then 10 to 19, and so on until it reaches 99. At that point the counter must roll over to 00. The parallel inputs should load any values from 0 to 9 on each digit. If a parallel binary input falls outside the valid BCD range (1010 to 1111) for either digit, the circuit should set that digit to 9 when the parallel input is loaded.