assistance reading BRAM from both the PL and PS
Budget: $30 – $250 USD
working with a Arty 7Z-20: Zynq-7000. The intent of the project is to create a functional uart, that will modify the IO of a custom IP and have both the VHDL and the software modify shared memory (BRAM) so that information can be passed back and fourth. The data shared between them are a few integers.
I've been able to create the project on the VHDL side with what I need. BRAM controller, BRAM, and a custom AXI4 peripheral with various IO for my specific project (General IO pins).
I've been able to create the project on the VHDL side with what I need. BRAM controller, BRAM, and a custom AXI4 peripheral with various IO for my specific project (General IO pins).