Xilinx Zynq 7020 - VHDL/Processor Application - Vivado 2019.1
Budget: $750 – $1,500 USD
I'm looking for a FPGA / Firmware engineer who has rich experience in FPGA and VHDL/verilog programming.
The board is a Zedboard (Z7020) connecting to the RF front-end (MAX2771 EK).
The project consists of
-) Creating in baremetal application a Vivado pipeline (2019.1) to collect RF data from the MAX2771 to be transferred to the FPGA side of the Zynq SoC
-) Optimise our code for GPS position real-time application (FFT / IFFT / Signal Correlation)
-) Provide documentation on the code
The board is a Zedboard (Z7020) connecting to the RF front-end (MAX2771 EK).
The project consists of
-) Creating in baremetal application a Vivado pipeline (2019.1) to collect RF data from the MAX2771 to be transferred to the FPGA side of the Zynq SoC
-) Optimise our code for GPS position real-time application (FFT / IFFT / Signal Correlation)
-) Provide documentation on the code