Verilog programming(traffic light controller)
Budget: $10 – $30 USD
I have a Verilog project and the code must be written/edited and the get tested(stimulated) using my test benches. you must use Modelsim to check if you've passed the tests(it says in the modelsim's transcript) and Quartus for obtaining the RTL diagram(once the code is written and compiling in modelsim, this part takes only 2mins).
PLEASE GO OVER THE INSTRUCTIONS FIRST.
starter files are in the testbench_and_starter_verilog folder.
The starter code and tes files are given. all you need to do is go over the instructions and ONLY edit the 2 files under the names: top_level.sv and or top_level_hint.sv.
You MUST NOT change any other files than the two top_level files.
PLEASE GO OVER THE INSTRUCTIONS FIRST.
starter files are in the testbench_and_starter_verilog folder.
The starter code and tes files are given. all you need to do is go over the instructions and ONLY edit the 2 files under the names: top_level.sv and or top_level_hint.sv.
You MUST NOT change any other files than the two top_level files.
Related categories:
Verilog / VHDL