Verilog Design for 10GbE on Artix Ultrascale+
Budget: ₹400 – ₹750 INR
I'm seeking a skilled FPGA developer with comprehensive knowledge in Verilog and Ethernet standards. The project involves implementing a 10 Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) and Media Access Control (MAC) in an Artix Ultrascale+ FPGA, utilizing SFP+ ports.
Key Responsibilities:
- Design and implement a Verilog module for basic data transmission via 10GbE.
- Ensure compatibility with Artix Ultrascale+ FPGA.
- Utilize Vivado for all simulations, testing and final implementation.
Ideal Candidates:
- Proficient in Verilog and FPGA design, particularly with Artix Ultrascale+ series.
- Extensive experience with designing Ethernet PCS/PMA and MAC layers.
- Familiar with Vivado and its simulation capabilities.
- Able to deliver efficient, reliable and well-documented code.
Key Responsibilities:
- Design and implement a Verilog module for basic data transmission via 10GbE.
- Ensure compatibility with Artix Ultrascale+ FPGA.
- Utilize Vivado for all simulations, testing and final implementation.
Ideal Candidates:
- Proficient in Verilog and FPGA design, particularly with Artix Ultrascale+ series.
- Extensive experience with designing Ethernet PCS/PMA and MAC layers.
- Familiar with Vivado and its simulation capabilities.
- Able to deliver efficient, reliable and well-documented code.