VLSI WITH VHDL or Verilog

Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties:
1- Addresses are from 0x8000 to 0x801F.
2- You can read and write one byte at a time.
3- The are special output signals that are required. They are listed in the table below.

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Requirement:
Phase 1:Part 1: Verify the design using a logic design tool and an HDL tool (VHDL or Verilog) using structural method
Part 2: List in a table the required components with their respective input and output labels.
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Phase 2:
Part 3: Implement your design using Magic VLSI layout tool to generate your project layout http://opencircuitdesign.com/magic/
Part 4: Test your design using irsim to simulate your project. http://opencircuitdesign.com/irsim/

phase 1 should be by Sunday

Deliverables:
TBD