VHDL design of a stopwatch
Budget: €30 – €250 EUR
I want someone to design a stopwatch in VHDL with a synthesizable project in Modelsim and final implementation in Xilinx ISE. The stopwatch should show on a character LCD and so the driver for the character LCD must also be written.
I will provide all the required documents and details and even the project structure but then I need assurance for timely delivery. The project must be tested on real Xilinx spartan hardware after synthesis.
Please only people wth experience ask for the project.
I will provide all the required documents and details and even the project structure but then I need assurance for timely delivery. The project must be tested on real Xilinx spartan hardware after synthesis.
Please only people wth experience ask for the project.