VHDL code fixing

Job ID: 32928066

Budget: $30 – $250 USD

I have created a code that uses 3 switches for operations and unsigned or signed. Also SW(12 downto 7): number1 (6 bits), SW(6 downto 0): number2 (7 bits). I created everything but I do not know what is wrong with my code. Can you help me?

Related categories: Verilog / VHDL Electrical Engineering FPGA