VHDL DESIGNER
Budget: $30 – $250 USD
• All the coursework has to be done in VHDL. Coursework handed in using another language will be
marked as zero.
• Coursework must be typeset.
• Never use screenshots or photograph of code in your coursework. Typeset code within your
coursework report using a monospace font (e.g. courier new).
• Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include
a high resolution screenshot in your coursework.
• The FPGA board is not required for this coursework
• Vivado is not necessary for this coursework (syntax errors will not penalise the evaluation).
marked as zero.
• Coursework must be typeset.
• Never use screenshots or photograph of code in your coursework. Typeset code within your
coursework report using a monospace font (e.g. courier new).
• Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include
a high resolution screenshot in your coursework.
• The FPGA board is not required for this coursework
• Vivado is not necessary for this coursework (syntax errors will not penalise the evaluation).
Related categories:
Verilog / VHDL