VHDL Code Development

Develop a VHDL program that outputs two preprogrammed sequences to 6 pins, see Fig. 1 in the attached PDF. One sequence is triggered on the rising edge and the other on the falling edge, see Fig. 2 in the attached PDF. Each sequence is 200 ns long, with 4 transitions and a target timing resolution of at least 2.5 ns per transition. Each transition must be repeatable to within 500 ps.