VHDL-Based Finite State Machine Design

I'm working on a digital circuit design project focused on a finite state machine (FSM) for a lock system. I need assistance with the design and implementation using VHDL on a Basys3 FPGA board.

Ideal Skills:
- Proficiency in VHDL
- Experience with digital circuit design
- Familiarity with FSMs

Key Tasks:
- Design a FSM for a lock system
- Implement the design using VHDL
- Test the design on a Basys3 FPGA board

Please provide examples of similar projects you've completed in your proposal.